This is where the various optimizing switches and their actions are described, grouped per switch.
with n = 1..4: these switches activate the optimizer. A higher level automatically includes all lower levels.
Level 1 (-O1) activates the peephole optimizer (common instruction sequences are replaced by faster equivalents).
Level 2 (-O2) enables the assembler data flow analyzer, which allows the common subexpression elimination procedure to remove unnecessary reloads of registers with values they already contain.
Level 3 (-O3) equals level 2 optimizations plus some time-intensive optimizations.
Level 4 (-O4) equals level 3 optimizations plus some optimizations which may have side effects.
Set alignment of X to Y.
Enable or disable specific optimizations; See section 1.2.60 on 155 for a list of possible values for XXX.
Set target cpu for optimizing to XXX; see fpc -i or fpc -ic for possible values.
Generate whole-program optimization feedback for optimization XXX see fpc -i or fpc -iw for possible values.
Perform whole-program optimization XXX; see fpc -i or fpc -iw for possible values.
Optimize for size rather than speed.
A more complete description of possible optimization switches can be found in section 1.2.60 on 155.